The present disclosure relates generally to integrated circuit design tools, and, in particular, to coupled noise timing violation avoidance in detailed routing.
As computer speeds have increased, and semiconductor technology dimensions have decreased, coupled noise effects on timing have correspondingly worsened. Faster switching speeds of advanced technologies have amplified higher frequency component contribution to signal spectra. An exchange of signal energy among capacitively coupled signal lines is most efficient for these higher frequencies. In addition, newer semiconductor technologies employ reduced lithography dimensions. The smaller shape sizes have resulted in reduced spacing between wires, and increased capacitive coupling between nets within integrated circuits.
As a result of these two effects, i.e., increased spectral coupling efficiency and increased capacitive coupling magnitude, advanced semiconductor technologies are becoming increasingly susceptible to coupled noise. Under the right circumstances of signal-to-signal synchronicity, a given amount of coupled noise energy results in a corresponding delay impact on signal timing. The probability that this change in delay will result in a timing violation increases as machine speeds increase and cycle times decrease. This situation develops because a given amount of noise-induced signal delta delay represents a greater threat to cycle time violation as the cycle times grow smaller, and the corresponding timing slack margins associated with those cycle time paths grow commensurately smaller as well.
The problem of minimizing the effect of coupled noise on design closure is often referred to in short hand as “noise avoidance”. This terminology can be misleading, as it is not strictly necessary to avoid the creation of noise in order to avoid the destructive effects of noise on design timing closure. It is often not possible to completely eradicate the sources of noise and still construct a viable design. While it is true that if there is no coupled noise, there can be no effect of noise on logic path timing, to achieve such a result, every signal path would be required to be completely isolated from all other signal paths. Such isolation is expensive in terms of design resources. Preventing wires from coupling electrically has generally involved minimizing their physical adjacency. Traditionally, isolation has been accomplished by spreading wires apart; however, this approach consumes valuable track resources in the process. Such spreading often results in lengthened signal nets and additional path delay due to the parasitic effects of the increased net lengths. As a result, in attempting to avoid increased path delay due to coupled noise, the spreading solution imposes an additional path delay burden of its own, which is the very result the process was trying to avoid.
Most wire routing tools today execute routing in a two-step process. In the first step, a lower resolution approximate routing model (abstraction) is created and utilized in a global routing pass to develop routing guidelines and constraints for the detailed wiring step to follow. In this first step, global pass wires are not routed to specific wiring tracks, but rather are confined to sets of wiring channels that represent the guidelines or constraints for eventual track assignment. In the second step, called a detail routing pass, each net is defined by routing through specific track assignments, which generally follow the guidelines established by the first step global pass constraints.
There have been a number of approaches to avoiding the effects of coupled noise on timing, ranging from indiscriminant detail routing with maximal spreading of detail wires, to low resolution global routing constraint control of probabilistic coupling among detail wires. The approaches share two common characteristics, they address the noise-coupling problem by indirect methods, and they do not fully exploit the potential to optimally control the physical coupling of wires without incurring a timing violation penalty. Each approach attempts to minimize the impact of noise coupling on timing closure by applying physical adjacency avoidance, which may reduce noise impact in a simple general abstract sense, but lacks the acuity to solve the problem surgically and directly on a case-by-case basis.
Current global routing noise avoidance solutions are only partially effective in reducing the amount of noise-induced timing violations. Yield-oriented detail router spreading is not discriminatory with respect to noise-induced timing failures. Any improvement in the coupled noise situation is haphazard, random, and statistically derived. Current detail routing methods do not target minimization of noise-induced timing violations. Thus, when performing detailed routing within an integrated circuit, it would be beneficial to develop a method for allowing and tolerating specific configurations of coupled noise that permit maximal routing freedom, without degrading the design's timing target closure capability. Accordingly, there is a need in the art for coupled noise timing violation avoidance in detailed routing of an integrated circuit.